Formal verification and performance evaluation of logic integrated systems based on hierarchical analysis

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986273

F. El-licy, H. Abdel-Aty-Zohdy

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Abstract

Formal verification of very large scale integrated circuit (VLSIC) involves the formal correctness of the functionality of a given design, while circuit validation involves the reliability and efficiency of the design. A hierarchical approach for computation, of IC design efficiency is proposed and implemented using figures of merit. The work has been motivated to partially complete an IC formal verification tool. The implemented system is integrated into a formal verification environment to reflect the performance of the verified system. The system is capable of analyzing the power dissipation and figures of merit using equivalent R and C components. The hierarchical analysis and evaluation of figures of merit general factors obtained at different system levels represent performance evaluation of each gate. An illustrative example of a 6/spl times/6 carry look-ahead adder is given and worst case conditions have been determined. The system performance may thus be improved.

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基于层次分析的逻辑集成系统形式化验证与性能评价

超大规模集成电路(VLSIC)的形式化验证涉及给定设计功能的形式化正确性，而电路验证涉及设计的可靠性和效率。提出了一种计算集成电路设计效率的分层方法，并利用优值图实现了该方法。这项工作的动机是部分完成IC形式化验证工具。已实现的系统被集成到正式的验证环境中，以反映已验证系统的性能。该系统能够使用等效的R和C分量来分析功耗和性能指标。在不同的系统层次上得到的优点一般因素的层次分析和评价数字代表了对每个门的性能评价。给出了一个6/spl × /6进位预判加法器的示例，并确定了最坏情况。这样可以提高系统的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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