A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage–Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs

Abstract

This letter presents a single-channel high-speed hybrid voltage–time two-step analog to digital converter (ADC). Two time-based converters (TBCs) are pipelined by a capacitive DAC (CDAC) and a residue amplifier (RA). The proposed hybrid architecture minimizes the impact of the TBCs nonlinearity while maintaining a low-power consumption for a high sample rate. A unipolar voltage to time converter (VTC) and a ring oscillator (RO)-based time to digital converter (TDC) with feed-forward and 2× interpolation is used as TBC which ensures high-speed and low-power operation. The prototype ADC is fabricated in 28-nm CMOS. At 4-GS/s and a Nyquist input frequency, it achieves 39.9-dB SNDR and 47.8-dB SFDR for a power consumption of 11.7 mW. The FOMW and FOMS are 36.2 fJ/conv-step and 152.2 dB, respectively.