The chip design for digital beam forming

Abstract

Digital beam forming (DBF) is the main computation in digital signal processors for radar and sonar systems. Conventional DBF is made up of multipliers and adders, but it cannot satisfy the need of real time processing because of its slow speed. In this paper, the authors introduce the distributed arithmetic (DA) algorithm for DBF. They find that the DBF circuit, according to the DA algorithm, is easy to realize in LSI with high speed and effective hardware. DBF chip has been designed using 3 mu m CMOS technology. The chip contains only 1000 gates and its data channels are changeable.<>