Left-shifter: A pre-silicon framework for usage model based performance verification of the PCIe interface in server processor system on chips

Abstract

Input/Output (IO) peripherals like storage devices and network interface cards play a significant role in determining the end user visible performance of many server applications. In addition, many server applications depend on accelerators to achieve the desired performance levels. PCIe is the de-facto standard used for connecting IO peripherals and accelerators to server processor System On Chips (SoC). Therefore, it is important to verify that PCIe interface(s) of a server processor SoC allows full utilization of the available PCIe link bandwidth with reasonable transaction latencies for PCIe traffic patterns corresponding to the most common ways in which PCIe IO devices and accelerators are used by applications. Currently, to the best of our knowledge, such IO and accelerator usage model based PCIe interface performance verification can only be done after the manufactured SoC is available (i.e., in post-silicon). Unfortunately, doing such verification in post-silicon means that if any serious performance issues are found, the SoC developer is forced to invest in costly rectification and remanufacturing of the SoC. In this paper, we introduce an emulation-based framework that enables a “shift-left” of usage model based PCIe interface performance verification from post-silicon to pre-silicon. In contrast to the current post-silicon-based approach, our framework offers a low cost, fast turnaround method to identify and fix PCIe related performance issues prior to manufacturing the chip.