Imed Yehyaoui, T. Frikha, Mohamed Abid, Hassen Drira
{"title":"Embedded adaptation for 3D face analysis using Elastic Riemannian algorithm","authors":"Imed Yehyaoui, T. Frikha, Mohamed Abid, Hassen Drira","doi":"10.1109/IDT.2016.7843016","DOIUrl":null,"url":null,"abstract":"Advanced algorithms are used today in multimedia applications and several other fields like wireless communication, medical treatments, defense systems, and a wide variety of consumer applications. These algorithms need more sophisticated systems than ever before. In the wide spreading virtual reality applications and 3D technologies, the need for fast and accurate 3D shape analysis computations, in the ever growing amount of 3D data and scanning systems performance, is steadily growing. In this paper, we propose a hardware acceleration of Elastic riemannian metrics computations for shape analysis used in a 3D face analysis context. The proposed architecture exploit the new concept of Dynamic partial reconfiguration by loading the accelerator in a specified reconfigurable partition, on a Xilinx Zynq-7000 integrated circuit, when needed. The reconfiguration is performed dynamically and partially without blocking or disturbing the rest of the system. The improved hardware acceleration shall enable high-performance computations with lower energy consumption while covering less area on the FPGA.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 11th International Design & Test Symposium (IDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDT.2016.7843016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Advanced algorithms are used today in multimedia applications and several other fields like wireless communication, medical treatments, defense systems, and a wide variety of consumer applications. These algorithms need more sophisticated systems than ever before. In the wide spreading virtual reality applications and 3D technologies, the need for fast and accurate 3D shape analysis computations, in the ever growing amount of 3D data and scanning systems performance, is steadily growing. In this paper, we propose a hardware acceleration of Elastic riemannian metrics computations for shape analysis used in a 3D face analysis context. The proposed architecture exploit the new concept of Dynamic partial reconfiguration by loading the accelerator in a specified reconfigurable partition, on a Xilinx Zynq-7000 integrated circuit, when needed. The reconfiguration is performed dynamically and partially without blocking or disturbing the rest of the system. The improved hardware acceleration shall enable high-performance computations with lower energy consumption while covering less area on the FPGA.