CMOS Simulation of Mixed-Polarity Generalized Fredkin Gates

Abstract

Processors have become increasingly overloaded with transistors in the last years. It causes heat dissipation and, as a result, error occurrence. One of the ways to solve those problems is to use reversible logic instead of the classical one. Therefore, reversible gates implemented in CMOS are valuable assets in electronic circuitry. The paper raises an approach for simulating generalized mixed-polarity Fredkin gate on CMOS transistors. Estimation formulas of complexity, delay, and power consumption were obtained for the circuits. A simulation of the proposed n-bit Fredkin gate with mixed control in Multisim 14.2 confirmed its functional correctness.