Delay testing and failure analysis of ECL logic with embedded memories

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208167

Kyle G. Welch, J. Monzel, D. Kent, Donald W. Joseph

引用次数: 1

Abstract

Two delay testing techniques, 'weighted random pattern' (WRP) test for logic and 'algorithmic pattern generation at the tester' (APG @ TT) for embedded memories are discussed. Several performance fails detected with these test techniques, escaping prior tests, are presented and potential failure modes predicted. AC probing techniques used to replicate the fails during failure analysis are featured.<>

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嵌入式存储器ECL逻辑的延迟测试与失效分析

讨论了两种延迟测试技术，即用于逻辑的“加权随机模式”(WRP)测试和用于嵌入式存储器的“测试器算法模式生成”(APG @ TT)。利用这些测试技术检测到的几种性能故障逃过了先前的测试，并预测了潜在的故障模式。在故障分析期间用于复制故障的交流探测技术具有特色

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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