An Ultra Low Power Pixel for Implantable Neural Interfaces

Abstract

The design of an 8 x 8 array in a 180 nm CMOS technology is presented for testing a new type of neural sensing amplifier. Post layout simulation results show an input refereed noise of 10.3 μVrms in the local field potential band from 1Hz to 300Hz and 19.8 μVrms in the action potential band from 300Hz to 10kHz. The required power per pixel is 165 nW or 50nA at 3.3 V. The bandwidth is 2kHz at a full frame rate of 10kHz.