{"title":"8-bit Low-Power, Low-Area SAR ADC for Biomedical Multichannel Integrated Recording System in CMOS 40nm","authors":"Magdalena Rosol, P. Kmon","doi":"10.23919/mixdes55591.2022.9837970","DOIUrl":null,"url":null,"abstract":"This paper presents the design and postlayout simu-lation results of 8-bit analog-to-digital converter (ADC) dedicated to multichannel biomedical integrated recording system. The integrated circuit is implemented in CMOS 40 nm process and has been recently received from fabrication. The proposed ADC is based on charge redistribution technique utilizing only two capacitors. The designed ADC converts analog signals provided from eight chopper based amplifiers, achieves sampling rate up to 1 M S / s and occupies only 0. 0033m m2 of silicon area. The peak DNL and INL are −0.6 and −1.4 LSB respectively. This paper presents particular blocks' detailed analysis as well as their postlayout simulation results.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/mixdes55591.2022.9837970","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the design and postlayout simu-lation results of 8-bit analog-to-digital converter (ADC) dedicated to multichannel biomedical integrated recording system. The integrated circuit is implemented in CMOS 40 nm process and has been recently received from fabrication. The proposed ADC is based on charge redistribution technique utilizing only two capacitors. The designed ADC converts analog signals provided from eight chopper based amplifiers, achieves sampling rate up to 1 M S / s and occupies only 0. 0033m m2 of silicon area. The peak DNL and INL are −0.6 and −1.4 LSB respectively. This paper presents particular blocks' detailed analysis as well as their postlayout simulation results.