A. Tripathi, M. Shah, S. Madhusoodhanan, S. Bhattacharya, K. Hatua
{"title":"FPGA based control board development for medium-voltage high-power three-phase dual active bridge converter","authors":"A. Tripathi, M. Shah, S. Madhusoodhanan, S. Bhattacharya, K. Hatua","doi":"10.1109/IECON.2014.7048698","DOIUrl":null,"url":null,"abstract":"A high power Y : Y/Δ three-phase Dual Active Bridge (DAB) topology offers higher power density, smaller switching stress, smaller volume of magnetics and smaller DC capacitor over single phase DAB. Therefore this topology is suitable for medium voltage (MV) applications. The high-frequency DAB currents are nearly sinusoidal suited for D-Q transformation which enables fast average mode current control for device protection. But it requires fast ADC conversions and processing speed to implement this control. Also the PWM channel requirement for this topology is high. A DSP repeats an infinite loop of calculations serially. Thus it has limited loop speed in case of longer algorithm size which limits the control bandwidth. An FPGA based control is suitable as it can process the algorithm in programmable combinational logic circuits which offer few nano-seconds of propagation delay. And thus the only speed limitation is the ADC conversion speed. But an FPGA board does not readily offer all the features required for this application. Therefore an ultra-fast 2 MSPS parallel ADC interface board has been developed to achieve the control objectives for the topology in this paper.","PeriodicalId":228897,"journal":{"name":"IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IECON.2014.7048698","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A high power Y : Y/Δ three-phase Dual Active Bridge (DAB) topology offers higher power density, smaller switching stress, smaller volume of magnetics and smaller DC capacitor over single phase DAB. Therefore this topology is suitable for medium voltage (MV) applications. The high-frequency DAB currents are nearly sinusoidal suited for D-Q transformation which enables fast average mode current control for device protection. But it requires fast ADC conversions and processing speed to implement this control. Also the PWM channel requirement for this topology is high. A DSP repeats an infinite loop of calculations serially. Thus it has limited loop speed in case of longer algorithm size which limits the control bandwidth. An FPGA based control is suitable as it can process the algorithm in programmable combinational logic circuits which offer few nano-seconds of propagation delay. And thus the only speed limitation is the ADC conversion speed. But an FPGA board does not readily offer all the features required for this application. Therefore an ultra-fast 2 MSPS parallel ADC interface board has been developed to achieve the control objectives for the topology in this paper.