A Novel Low-Dropout Regulator with Dynamically-biased Current and Super Source Follower

Abstract

Low-Dropout (LDO) regulator is a key component widely used in integrated on-chip power management devices requiring a clean supply voltage and small area. The stability is a crucial performance parameter since the dominant pole and other high-frequency poles will vary with different load conditions. The load transient quantifies the peak output-voltage excursion and settling time of signals when the load current is stepped. An LDO regulator with a good load-transient response must achieve a minimal overshoot/undershoot voltage and fast settling time by placing an off-chip capacitor or increasing the bias current to improve the transient response. Also, the quiescent current should be considered in designing the LDO regulator.