A Complementary Half-Swing Bus Architecture and its Application for Wide Band SRAM Macro

Abstract

A complementary half-swing bus architecture is proposed for high speed and low power operation. The bus is composed of pairs of lines. The bus operates with three steps every cycle. In the first two steps, both bus lines within a pair are set at a half of the supply voltage. In the last step, each bus level is determined independently according to their data whether it is driven to the supply voltage or ground level, or remains unchanged. Then, each bus line swings the upper or lower half of the supply voltage exclusively. This simple architecture is able to transfer data in mutual direction at higher speed without an area penalty. It is applied to an SRAM macro with 112-bit bus for an ATM switch LSI. The 84 K-bit macro is fabricated in an area of 3.5 mm/spl times/4.2 mm with a 0.5 /spl mu/m CMOS process technology. Experimental results indicate that it operates beyond 200 MHz at the supply voltage of 3.3 V. From a cross-talk consideration, the cross-talk works such as to enlarge the operation margin. Simulation results show that the worst case power dissipation and the peak current due to simultaneous switching are reduced by half and by 66%, respectively, compared with full swing architectures.