L. Maurer, G. Hueber, T. Dellsperger, T. Burger, M. Huemer, R. Weigel
{"title":"A frequency agile terminal receiver for wireless multi-standard applications","authors":"L. Maurer, G. Hueber, T. Dellsperger, T. Burger, M. Huemer, R. Weigel","doi":"10.1109/RWS.2006.1615152","DOIUrl":null,"url":null,"abstract":"This paper presents a flexible multi-standard receiver architecture that extends the well known direct conversion receiver (DCR). With high dynamic-range/low-power sigma-delta analog-to-digital converters (ADC) and digital signal processing functions locally on the radio frequency integrated circuit (RFIC) a receiver with relaxed requirements for the analog part and a flexible bandwidth channel filtering in digital domain can be realized. Furthermore, the architecture introduces a digital interface between RF and digital baseband IC. Since analog building blocks have limited reconfiguration capabilities by nature of their implementation, the extension of the conventional analog signal processing blocks by a digital front-end (DFE) greatly enhances the flexibility of the RFIC. Measurements of a prototype implementation of the proposed receiver architecture are presented","PeriodicalId":244560,"journal":{"name":"2006 IEEE Radio and Wireless Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2006.1615152","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper presents a flexible multi-standard receiver architecture that extends the well known direct conversion receiver (DCR). With high dynamic-range/low-power sigma-delta analog-to-digital converters (ADC) and digital signal processing functions locally on the radio frequency integrated circuit (RFIC) a receiver with relaxed requirements for the analog part and a flexible bandwidth channel filtering in digital domain can be realized. Furthermore, the architecture introduces a digital interface between RF and digital baseband IC. Since analog building blocks have limited reconfiguration capabilities by nature of their implementation, the extension of the conventional analog signal processing blocks by a digital front-end (DFE) greatly enhances the flexibility of the RFIC. Measurements of a prototype implementation of the proposed receiver architecture are presented