Modified Low Power High Speed Approximate Adders For Energy Efficient Arithmetic Applications

Abstract

The suggested circuits are crucial for increasing the effectiveness of circuit design in approximate computing since they are related to the design of approximate full adders for energy-efficient arithmetic applications. Adders, which are essential to computing machines, are composed of the building blocks of arithmetic circuitry. Digital signal processing applications commonly use arithmetic circuits, based on MOSFET technology. Using the Cadence Virtuoso tool and 45 nm CMOS technology, the suggested new designs are simulated. The proposed innovative circuits are examined and evaluated using Cadence Software for latency, power consumption, and mistakes.