Optimizing pattern fill for planarity and parasitic capacitance

Abstract

Chemical mechanical polishing causes dishing in the planarized layer causing significant topographical challenges for subsequent patterning. One solution for dishing phenomenon is introduction of metal pattern fill with dummy structures as a method to improve planarity for a given layer. This paper deals with the optimization of planarity and parasitic capacitance. Wafer level topography maps illustrates the planarity of circuit without pattern fill. Parasitic capacitance analysis is performed by closed form solution. Using the analysis of the circuit-level parasitic capacitance tool, the estimated effect on various circuit nets is calculated.