Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture

Abstract

With the increase in complexity of fabrication techniques, yield of the chip production decreases at deep sub-micron technologies. In future fault tolerant techniques will be important to increase the yield of the VLSI chips in advanced fabrication technologies. In regular structure like FPGA, redundancy is commonly used for fault tolerance. Most of the techniques found so far in literature talk about software based changes in the configuration data. In this work we present a solution in which configuration bit stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant columns for replacing faulty cells. Experiments on different circuits using VPR tool shows that there is an average 2.6% increase in the critical path delay while no increase in the area per cell due to our approach.