A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory

Abstract

A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.