A novel MDCT/IMDCT computing kernel design

Abstract

This paper presents a novel MDCT/IMDCT algorithm and its hardware design. In algorithm derivation, the MDCT/IMDCT computation is first converted into a form of matrix multiplication consisting of a half size DCT-IV kernel and a projection matrix. The DCT-IV kernel is then realized by a fast DCT-II computing scheme. Since MDCT and IMDCT algorithms use the same DCT kernel, a unified architecture using the same set of twiddle factors can be employed for both computations. Based on the proposed algorithm, a novel design mapping is developed with emphasis on the reduction of hardware and memory access complexities. By careful scheduling in computation and memory access schemes, only single port memory modules are needed in lieu of expensive dual port memories. Performance analyses reveal that, given the comparable hardware resource allocation, the proposed design can outperform other MDCT/IMDCT designs in terms of memory storage size, computing latency and fixed point implementation error.