A Symbolic Functional Description Language

Abstract

This paper describes a new diagrammatic hardware description language SFDL (Symbolic Functional Description Language) and a hierarchical logic design supporting system LDSS (Logic Design Supporting System). SFDL has three features that help designers design logic circuits easily and speedily; easy to describe with its simple rule, comprehensible to grasp the behavior of the circuit and suitable for computer processing. Besides, the LDSS allows designers to draw diagrams without the attention to complicated drawing rule and translate the SFDL diagrams into a text-styled hardware description language. Through experiments, the effectiveness of the SFDL for hierarchical logic design has been confirmed.