Design and Performance Analysis on Static and Dynamic Pipelined CPU in Course Experiment of Computer Architecture

Abstract

This paper presents a design method of static pipelined CPU and dynamic pipelined CPU with field programable gate array (FPGA) in the computer architecture course. This course experiment project is a five-stage pipelined 32-bit MIPS design on a Nexys 4 board. It is more difficult to directly design and implement a pipelined CPU. The design methods of the two pipelined CPUs in this paper are based on the implemented single-cycle CPU for modification and redevelopment, which is convenient and easy to implement. The goal of the project is to help students successfully complete the design and implementation of static and dynamic pipelined CPUs, and help students thoroughly understand the working principle of the pipelined CPU through performance analysis. According to the design method, students have independently designed and implemented a static and dynamic pipelined CPU, and compared the performance of the two types of CPUs at the same time, which reveals the effectiveness of the method.