Design considerations and device selection in the implementation of low phase noise LC-VCOs

Abstract

This paper presents a comparative study on the difference in the performance of a differential negative resistance LC-VCO when CMOS and bipolar transistors are used in its implementation. Both the noise magnitude of these transistors and the noise up-conversion mechanisms are used to identify the best selection of devices in designing a low phase noise LC-VCO. This study was performed using the IHP 0.25 mum SiGe BiCMOS process and the LC-VCO design is targeted for a Bluetooth transceiver application. I.