A 120 MHz SC 4th-order elliptic interpolation filter with accurate gain and offset compensation for direct digital frequency synthesizer

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824010

U. Seng-Pan, R. Neves, R. Martins, J. Franca

引用次数: 1

Abstract

This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation achieved by Predictive Correlated-Double Sampling techniques. This filter is designed with optimized speed of the analog components in AMS 0.35 /spl mu/m CMOS technology, occupies about 0.4 mm/sup 2/ active area and consumes about 22 mW at 3.0 V supply.

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用于直接数字频率合成器的具有精确增益和偏移补偿的120mhz SC四阶椭圆插值滤波器

本文提出了一种用于直接数字频率合成器系统的高频开关电容IIR插值滤波器的优化设计。该电路由新型双采样递归直接形式II和非递归多相结构组合而成，该结构嵌入无失匹配的模拟延迟线，并通过预测相关双采样技术实现精确的宽带增益和偏移补偿。该滤波器采用AMS 0.35 /spl mu/m CMOS技术优化模拟元件的速度，在3.0 V电源下占用约0.4 mm/sup / 2/有源面积，功耗约22 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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