High Speed Video Processing Using Fine-Grained Processing on FPGA Platform

Z. Ang, Akash Kumar, Yajun Ha
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引用次数: 7

Abstract

This summary paper1 proposes an FPGA-based array processor which performs Laplacian filtering on a 40 by 40 pixel grayscale video. The architecture comprises of bit-serial pixel processors interconnected to give a two-dimensional mesh array. This architecture features the novel use of partial reconfiguration which transfers data to and fro the array. Each processor occupies a configurable logic block and achieves a target frame rate of 10000 frames per second, at an operating frequency of 0.31 MHz on the Virtex-6 ML605 Evaluation Kit. The detailed correspondence between the contents of slice lookup tables and the Virtex-6 bitstream format is also documented.
基于FPGA平台的细粒度高速视频处理
本文提出了一种基于fpga的阵列处理器,对40 × 40像素的灰度视频进行拉普拉斯滤波。该体系结构由位串行像素处理器组成,这些处理器相互连接以形成二维网格阵列。该体系结构的特点是采用了局部重构的新方法,可以在数组之间来回传输数据。每个处理器占用一个可配置的逻辑块,在Virtex-6 ML605评估套件上实现每秒10000帧的目标帧率,工作频率为0.31 MHz。切片查找表的内容和Virtex-6位流格式之间的详细对应关系也被记录下来。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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