Ning Ma, Zhibo Pang, Jun Chen, H. Tenhunen, Lirong Zheng
{"title":"A 5Mgate/414mW networked media SoC in 0.13um CMOS with 720p multi-standard video decoding","authors":"Ning Ma, Zhibo Pang, Jun Chen, H. Tenhunen, Lirong Zheng","doi":"10.1109/ASSCC.2009.5357177","DOIUrl":null,"url":null,"abstract":"A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet interface and coarse-grained configurable video decoding unit. Real-time 1280×720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with die size of 6.4mm × 6.4mm. To achieve low power design, flexible power management strategy is implemented including dynamic configuration of clock frequency synthesis and module level clock gating according to the workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280×720@25fps) video streams are decoded. The power consumption is reduced to 95mW for real-time CIF (352×288@25fps) video stream decoding at 27MHz system frequency.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357177","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet interface and coarse-grained configurable video decoding unit. Real-time 1280×720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with die size of 6.4mm × 6.4mm. To achieve low power design, flexible power management strategy is implemented including dynamic configuration of clock frequency synthesis and module level clock gating according to the workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280×720@25fps) video streams are decoded. The power consumption is reduced to 95mW for real-time CIF (352×288@25fps) video stream decoding at 27MHz system frequency.