A pipelined time stretching for high throughput counter-based time-to-digital converters

Abstract

This paper proposes a pipelined time stretching technique for high throughput counter-based time-to-digital converters (TDC). Time stretching technique is used to increase the resolution of counter-based TDCs, yet it carries an inherent weakness of having a long conversion time due to the stretching phase. Without significant increment of chip area, the proposed pipelined time stretching method is realized with addition of a time splitter, a switching circuit and a fine capacitor. Pipelining of sampling and stretching efficiently improves the conversion rate by 29% according to the simulation results with a TSMC 0.25μm CMOS process.