Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion

R. Venkatesan, Jeffrey A. Davis, K. Bowman, J. Meindl
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引用次数: 8

Abstract

Minimum power CMOS ASIC macrocells are designed by minimizing the macrocell area using a new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures. The minimum macrocell area and power dissipation are projected for the 100, 70 and 50 nm technology generations and compared with a n-tier design without using repeaters. Repeater insertion and a novel interconnect geometry scaling technique decrease the power dissipation by 58-68% corresponding to a macrocell area reduction of 70-78% for the global clock frequency designs of these three technology generations.
使用最佳中继器插入的最小功率和面积n层多层互连架构
最小功耗CMOS ASIC宏单元是通过最小化宏单元面积来设计的,使用一种新的方法来优化插入n层多层互连架构的中继器。预测了100、70和50纳米技术的最小宏蜂窝面积和功耗,并与不使用中继器的n层设计进行了比较。对于这三代技术的全球时钟频率设计,中继器插入和新颖的互连几何缩放技术可将功耗降低58-68%,对应于宏小区面积减少70-78%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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