VHDLSFI: A simulation-based multi-bit fault injection for dependability analysis

Abstract

Decreasing technology sizing makes the CMOS devices more error prone to alpha particles and cosmic radiation. Therefore, the probability of occurring multi faults in such devices is increasing. This paper presents a simulation-based multi-bit fault injection tool, named VHDLSFI, aiming at conducting multi-bit fault injection campaign to analyze the dependability of digital systems modeled by VHDL description language. This fault injection tool utilizes the Force and Release statements which are features in the VHDL 2008 standard to inject transient and permanent single and multi-bit faults. Different fault models are developed using force and release statements. A VHDL model of DP32 processor is evaluated by this fault injection tool to demonstrate its functionality. A total of 2000 single faults and 7000 double faults have been injected into the ALU, Register File, General Registers, and different Buses in the processor using VHDLSFI fault injection tool. Only one single or one double fault is injected in each run. The results show that the percentages of errors propagation vary between 7% and 89% depending on single or double faults, the different workload programs, and location of the injected faults in the processor. The error propagation latency is much lower when the double faults in injected in DP32 processor.