Brief Announcement: Preserving Happens-before in Persistent Memory

Joseph Izraelevitz, H. Mendes, M. Scott
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引用次数: 16

Abstract

Nonvolatile, byte-addressable memory (NVM) will soon be commercially available, but registers and caches are expected to remain transient on most machines. Without careful management, the data preserved in the wake of a crash are likely to be inconsistent and thus unusable. Previous work has explored the semantics of instructions used to push the contents of cache to NVM. These semantics comprise a "memory persistency model," analogous to a traditional "memory consistency model." In this brief announcement we introduce "explicit epoch persistency", a memory persistency model that captures the current and expected semantics of Intel x86 and ARM v8 persistent memory instructions. We also present a construction that augments any data-race-free program (for release consistency or any stronger memory model) in such a way that preserved data are guaranteed to represent a consistent cut in the happens-before graph of the program's execution.
简短声明:在持久内存中保存之前发生的事情
非易失的、字节可寻址的内存(NVM)很快就会在商业上可用,但是寄存器和缓存在大多数机器上仍然是暂时的。如果不小心管理,在崩溃后保存的数据可能不一致,从而无法使用。以前的工作已经探索了用于将缓存内容推送到NVM的指令的语义。这些语义组成了一个“内存持久性模型”,类似于传统的“内存一致性模型”。在这篇简短的声明中,我们介绍了“显式epoch持久性”,这是一种内存持久性模型,可以捕获Intel x86和ARM v8持久内存指令的当前和预期语义。我们还提出了一种结构,它以这样一种方式增强任何无数据竞争的程序(用于释放一致性或任何更强的内存模型),即保证保留的数据在程序执行的happens-before图中表示一致的cut。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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