{"title":"Current-mode CMOS realization of a multiple-valued logic neurode","authors":"M. Abd-El-Barr, R. Bolton, A.K. Jain","doi":"10.1109/WESCAN.1993.270575","DOIUrl":null,"url":null,"abstract":"A new circuit is proposed for the realization of a multiple-valued logic (MVL) neurode, an electronic approximation of a human neuron, in a current-mode CMOS logic (CMCL) technology. A set of multiple-valued logic operators is presented. These operators include min, tsum, window literal, cycle, and complement. Basic circuits used to realize the MVL-neurode are also given. HSPICE simulation results to verify the operation of the MVL-neurode circuit are reported.<<ETX>>","PeriodicalId":146674,"journal":{"name":"IEEE WESCANEX 93 Communications, Computers and Power in the Modern Environment - Conference Proceedings","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE WESCANEX 93 Communications, Computers and Power in the Modern Environment - Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WESCAN.1993.270575","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A new circuit is proposed for the realization of a multiple-valued logic (MVL) neurode, an electronic approximation of a human neuron, in a current-mode CMOS logic (CMCL) technology. A set of multiple-valued logic operators is presented. These operators include min, tsum, window literal, cycle, and complement. Basic circuits used to realize the MVL-neurode are also given. HSPICE simulation results to verify the operation of the MVL-neurode circuit are reported.<>