An efficient post-processing method for pipelined pseudo-random number generator in SoC-FPGA

Abstract

Pseudo-random number generators (PRNGs) are one of the common parts of digital systems used in cryptography, diagnostics, simulation and in many other areas of modern science and technology. Here we present a novel architecture of the PRNG based on the chaotic nonlinear model and pipelined data processing. A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx and verified by standard statistical tests NIST SP800-22. For PRNGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRNG implementation in the programmable SoC device. The maximum output throughput of the proposed PRNG is equal to 38.44 Gbps and is significantly greater comparing to the chaotic PRNGs described so far.