A sequencing circuit to provide power up/down sequence to multiple outputs of a dc-dc converter for space application

A. Anand, Shreeti Goyal, Shivaprakash B, K. Gupta
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Abstract

In multi-rail complex power systems of loads like ASICs, FPGAs, DSPs, GaAs FET based Solid State Power Amplifier (SSPA), very specific power up and power down sequencing of different rail supplies is required, in order to guarantee reliable operation of these devices. For example, GaAs FET based SSPA has a special requirement that at Turn ON, output voltages should appear in a sequence of first −5V, then +8V followed by +15V. During turn OFF, +8V first, then +15V and last −5V should go low. This special requirement is because the GaAs FET used in SSPA is depletion type FET which requires a negative Gate bias (−5V) first and then Drain supply (+8V). Drain supply without proper gate bias may result in excessive drain current leading to the failure of GaAs FET. +15V O/P which supplies power to RF generator circuit, appearing after +8V will ensure input signal to amplifier after establishing the supply. Making an independent ‘Output Sequencing circuit’ proposed in this paper, offers advantages as follows: (a) It can be planned as a part of user package and can be used with any DC-DC converter which meets the load current/voltage requirements. (b) If there is a short circuit at DC-DC converter O/P, the converter will enter its own current limit protection. If the short circuit/ overload is at Load end on +15V or +8V line, DC-DC will enter its own current limit protection. Overload or short circuit on −5V O/P (>85mA) will result in turn OFF of all the O/Ps. Hence the sequence of outputs during turn ON & turn OFF is guaranteed (c) +15V O/P will never appear earlier than +8V O/P. (d) +8V O/P has internal low drop out regulator (LDO) to give very tight regulation for load range of 0.2A to 2A. No overshoot/ undershoot during load transient of +8V, hence this circuit supports large load transients on +8V output. The hardware circuit was realized & has successfully completed all the tests. This circuit has been realized in HMC form to reduce size and ease of accommodation in user packages.
一种时序电路,为空间应用的dc-dc转换器的多个输出提供电源上/下顺序
在asic, fpga, dsp,基于GaAs FET的固态功率放大器(SSPA)等负载的多轨道复杂电源系统中,需要非常具体的不同轨道电源的上电和下电顺序,以保证这些设备的可靠运行。例如,基于GaAs FET的SSPA有一个特殊的要求,即在ON时,输出电压应以先−5V,然后+8V,然后+15V的顺序出现。在关闭期间,+8V首先,然后+15V和最后- 5V应该变低。这一特殊要求是因为SSPA中使用的GaAs FET是耗尽型FET,首先需要负栅极偏压(- 5V),然后需要漏极电源(+8V)。漏极电源没有适当的栅极偏压可能导致漏极电流过大而导致GaAs场效应管失效。+15V O/P为射频发生器电路供电,+8V后出现,保证电源建立后放大器的输入信号。本文提出了一个独立的“输出时序电路”,具有以下优点:(a)它可以作为用户包的一部分进行规划,并且可以与任何满足负载电流/电压要求的DC-DC变换器一起使用。(b)如果DC-DC变换器O/P处发生短路,变换器将进入自身限流保护。如果短路/过载在+15V或+8V线路的负载端,DC-DC将进入自己的限流保护。−5V O/P (>85mA)过载或短路将导致所有O/P关闭。因此,在打开和关闭期间的输出顺序是保证的(c) +15V O/P将永远不会出现在+8V O/P之前。(d) +8V O/P具有内部低降稳压器(LDO),为0.2A至2A的负载范围提供非常严格的调节。负载暂态+8V时无过调/欠调,因此该电路支持+8V输出的大负载瞬态。实现了硬件电路,并成功完成了所有测试。该电路以HMC形式实现,以减小尺寸并便于用户封装。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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