{"title":"A sequencing circuit to provide power up/down sequence to multiple outputs of a dc-dc converter for space application","authors":"A. Anand, Shreeti Goyal, Shivaprakash B, K. Gupta","doi":"10.1109/CONECCT52877.2021.9622546","DOIUrl":null,"url":null,"abstract":"In multi-rail complex power systems of loads like ASICs, FPGAs, DSPs, GaAs FET based Solid State Power Amplifier (SSPA), very specific power up and power down sequencing of different rail supplies is required, in order to guarantee reliable operation of these devices. For example, GaAs FET based SSPA has a special requirement that at Turn ON, output voltages should appear in a sequence of first −5V, then +8V followed by +15V. During turn OFF, +8V first, then +15V and last −5V should go low. This special requirement is because the GaAs FET used in SSPA is depletion type FET which requires a negative Gate bias (−5V) first and then Drain supply (+8V). Drain supply without proper gate bias may result in excessive drain current leading to the failure of GaAs FET. +15V O/P which supplies power to RF generator circuit, appearing after +8V will ensure input signal to amplifier after establishing the supply. Making an independent ‘Output Sequencing circuit’ proposed in this paper, offers advantages as follows: (a) It can be planned as a part of user package and can be used with any DC-DC converter which meets the load current/voltage requirements. (b) If there is a short circuit at DC-DC converter O/P, the converter will enter its own current limit protection. If the short circuit/ overload is at Load end on +15V or +8V line, DC-DC will enter its own current limit protection. Overload or short circuit on −5V O/P (>85mA) will result in turn OFF of all the O/Ps. Hence the sequence of outputs during turn ON & turn OFF is guaranteed (c) +15V O/P will never appear earlier than +8V O/P. (d) +8V O/P has internal low drop out regulator (LDO) to give very tight regulation for load range of 0.2A to 2A. No overshoot/ undershoot during load transient of +8V, hence this circuit supports large load transients on +8V output. The hardware circuit was realized & has successfully completed all the tests. This circuit has been realized in HMC form to reduce size and ease of accommodation in user packages.","PeriodicalId":164499,"journal":{"name":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT52877.2021.9622546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In multi-rail complex power systems of loads like ASICs, FPGAs, DSPs, GaAs FET based Solid State Power Amplifier (SSPA), very specific power up and power down sequencing of different rail supplies is required, in order to guarantee reliable operation of these devices. For example, GaAs FET based SSPA has a special requirement that at Turn ON, output voltages should appear in a sequence of first −5V, then +8V followed by +15V. During turn OFF, +8V first, then +15V and last −5V should go low. This special requirement is because the GaAs FET used in SSPA is depletion type FET which requires a negative Gate bias (−5V) first and then Drain supply (+8V). Drain supply without proper gate bias may result in excessive drain current leading to the failure of GaAs FET. +15V O/P which supplies power to RF generator circuit, appearing after +8V will ensure input signal to amplifier after establishing the supply. Making an independent ‘Output Sequencing circuit’ proposed in this paper, offers advantages as follows: (a) It can be planned as a part of user package and can be used with any DC-DC converter which meets the load current/voltage requirements. (b) If there is a short circuit at DC-DC converter O/P, the converter will enter its own current limit protection. If the short circuit/ overload is at Load end on +15V or +8V line, DC-DC will enter its own current limit protection. Overload or short circuit on −5V O/P (>85mA) will result in turn OFF of all the O/Ps. Hence the sequence of outputs during turn ON & turn OFF is guaranteed (c) +15V O/P will never appear earlier than +8V O/P. (d) +8V O/P has internal low drop out regulator (LDO) to give very tight regulation for load range of 0.2A to 2A. No overshoot/ undershoot during load transient of +8V, hence this circuit supports large load transients on +8V output. The hardware circuit was realized & has successfully completed all the tests. This circuit has been realized in HMC form to reduce size and ease of accommodation in user packages.