B.C.D. multipliers

Abstract

B.C.D. versions of known multiplier designs are presented; both achieve fast multiplication times without the high hardware cost typically associated with high speed. Serial b.c.d. addition and r.o.m. single-digit multipliers permit the substantial reductions in hardware cost, while higher clock frequencies offset the inherent slowness of the serial methods. Greatest cost-effectiveness is seen to be achieved through l.s.i. implementationn of a serial design which is easily extended for higher radix b.c.d. multiplication.