J. Podivínský, Ondrej Cekan, Martin Krcma, Radek Burget, Tomás Hruska, Z. Kotásek
{"title":"A Processor Optimization Framework for a Selected Application","authors":"J. Podivínský, Ondrej Cekan, Martin Krcma, Radek Burget, Tomás Hruska, Z. Kotásek","doi":"10.1109/EWDTS.2018.8524733","DOIUrl":null,"url":null,"abstract":"A processor plays the main role in almost every electronic system. The use of a general purpose processor may not be suitable for a specific application, because the processor is designed for a wide set of applications. The Application-Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where a single application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking the possible configurations of its key parameters (such as the number of registers, cache sizes, instruction set modifications, etc.). The paper also presents a designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modeling and evaluation, the Codasip Studio tool is used. It allows to generate all the tools necessary for compilation, simulation, and hardware mapping which are used in the process of the ASIP design. The experiments are carried out on a RISC- V (Reduced Instruction Set Computing) processor.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2018.8524733","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A processor plays the main role in almost every electronic system. The use of a general purpose processor may not be suitable for a specific application, because the processor is designed for a wide set of applications. The Application-Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where a single application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking the possible configurations of its key parameters (such as the number of registers, cache sizes, instruction set modifications, etc.). The paper also presents a designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modeling and evaluation, the Codasip Studio tool is used. It allows to generate all the tools necessary for compilation, simulation, and hardware mapping which are used in the process of the ASIP design. The experiments are carried out on a RISC- V (Reduced Instruction Set Computing) processor.