{"title":"Chip design of a 5.6-GHz 1-V wide tuning range frequency synthesizer with Gm-boosting Colpitts VCO for biomedical application","authors":"Jhin-Fang Huang, W. Lai, Jia-Lun Yang","doi":"10.1109/ISBB.2014.6820899","DOIUrl":null,"url":null,"abstract":"A 5.6-GHz 1-V wide tuning range frequency synthesizer with a gain-boosting Colpitts voltage-controlled oscillator (VCO) is fabricated in TSMC 0.18 um CMOS process. In this prototype, there are two important features. First, a 1-V gain-boosting Colpitts LC VCO circuit is adopted to reduce phase noise and power consumption. Second, a class-AB current mode logic (CML) circuit is utilized in first divider stage to deal with the high frequency signal. At the supply voltages of 1-V for VCO and 1.8-V for digital circuits, measured results achieve that the VCO output frequency is tunable from 5.13~5.98 GHz corresponding to 15.4% and the locked phase noise is -105.83 dBc/Hz at 1MHz from 5.15 GHz. The power consumption is 5.6 mW and including pads, the chip area is 0.632 (0.89 × 0.71) mm2. This chip design low power consumption for biomedical application.","PeriodicalId":265886,"journal":{"name":"2014 IEEE International Symposium on Bioelectronics and Bioinformatics (IEEE ISBB 2014)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Symposium on Bioelectronics and Bioinformatics (IEEE ISBB 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISBB.2014.6820899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
A 5.6-GHz 1-V wide tuning range frequency synthesizer with a gain-boosting Colpitts voltage-controlled oscillator (VCO) is fabricated in TSMC 0.18 um CMOS process. In this prototype, there are two important features. First, a 1-V gain-boosting Colpitts LC VCO circuit is adopted to reduce phase noise and power consumption. Second, a class-AB current mode logic (CML) circuit is utilized in first divider stage to deal with the high frequency signal. At the supply voltages of 1-V for VCO and 1.8-V for digital circuits, measured results achieve that the VCO output frequency is tunable from 5.13~5.98 GHz corresponding to 15.4% and the locked phase noise is -105.83 dBc/Hz at 1MHz from 5.15 GHz. The power consumption is 5.6 mW and including pads, the chip area is 0.632 (0.89 × 0.71) mm2. This chip design low power consumption for biomedical application.