A new high-speed SAR ADC architecture

Abstract

The design plan and HSPICE measurement of a high acquisition speed for a sample of 8-bit CMOS differential successive approximation register (SAR) Analog-to-digital converter (ADC) are presented. The operation of the conventional main switch-capacitor array is divided into two switch-capacitor arrays. Such that, one switched-capacitor array is used to define the four most-significant bits, while the other switched-capacitor array is used to refine the digital output by measuring the least four significant bits. Thus, the critical time constant, which is usually realized in a single conversion cycle, is divided into four conversion cycles (i.e. the time required to quantize the four most-significant bits). Thereby, our proposed ADC operates at 200MHz conversion cycle for a sample rate of 25 MS/sec. with power consumption of 3.7mW. The design is based on 0.25µm CMOS TSMC technology and comprises three comparator circuits, sign-comparator and two switched-capacitor arrays' comparators.