Design of 1.8V LVDS Transmitter in GF 22nm For Associative Memory

K. R. Teja, G. V. Mallikarjuna Reddy, Subhakumar Reddy A
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引用次数: 2

Abstract

This paper presents the design of Low Voltage Differential Signaling (LVDS) transmitter for Associative Memory (AM). AM is used in High Energy Physics (HEP) experiments like Large Hadron Collider (LHC). AM can store up to one billion patterns. The proposed design works for IO supply of 1.8V and core supply of 1V with an output voltage swing of 350mV over 1.2V offset voltage. This design is implemented in 22nm FDSOI technology to work across process corners and is simulated using cadence virtuoso tool. This design is met the required data rate of 1Gbps for AM application with power consumption of 12.34mW.
用于联想存储器的GF 22nm 1.8V LVDS发射机设计
本文介绍了一种用于联想记忆(AM)的低压差分信号(LVDS)发送器的设计。AM用于大型强子对撞机(LHC)等高能物理(HEP)实验。AM可以存储多达10亿个图案。本文设计的IO电源为1.8V,核心电源为1V,在1.2V偏置电压下输出电压摆幅为350mV。该设计采用22nm FDSOI技术实现,可跨工艺角工作,并使用cadence virtuoso工具进行模拟。本设计满足了AM应用所需的1Gbps数据速率,功耗为12.34mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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