Synthesizable Assertion in Hardware and Software Development

Abstract

Assertion Based Validation (ABV) is an approach in which the design intent is captured in an executable form where all the out of range and missing intent intents will trigger an error which indicates the fall-outs. By using these assertions can enable early detection of very basic software and hardware bugs in the design. System Verilog is a hardware description language that combine with verification and commonly used as assertion language with its powerful assertion function embedded in the language itself. However not all system verilog language can be synthesize into hardware component and because of the limitation, it only use in software simulation phase of a design cycle. The approach to enable the ABV module in system verilog format to be synthesized into a portion of the hardware is the intent of this paper. It defines the synthesizable building blocks of the assertion modules. This can utilized by both hardware and software development in pre-silicon stage through reconfigurable hardware or Field Programmable Gate Array (FPGA). In hardware debug, the synthesized assertions will point to the area of failure, reducing the scope of debug. In software development, the synthesized assertions will point to invalid configurations of hardware registers. The assertions will be synthesized into a separate hardware block which is programmed into a reconfigurable hardware or FPGA together with the Design-Under-Test (DUT). The assertion validation hardware block consists of a 'Detection and Distribution' block and a series of 'Property Tracking' block to track the multiple events separately. If all separate events are met but the expected scenario is not met, a register bit will be set for this assertion point to signify failure. Final assertion results will be written to memory on the reconfigurable hardware or FGPA. The purpose of this paper is to identify the common assertion function that widely use in hardware design and synthesis of these assertion properties from SVA to verilog structure.