Digital Image Scrambling Using Chaotic Systems Based on FPGA

Abstract

Image scrambling is one of the encryption techniques which is used to change the pixels’ position instead of changing pixels’ values. In this paper, an implementation of image scrambling by using chaotic flow sequences in FPGA is presented. The proposed system depends on transforming image dimension into vectors then the chaotic system is implemented on the transformed image to produce the scrambled image using the FPGA kit. FPGA Spartan-3A DSP 3400A hardware platform is used for the proposed system, where the testing image is in size 20 * 20 RGB digital image. The proposed system is the first image scrambled system that could be implemented in FPGA.