Generalization of clock gating logic using wide spread adapting technique

Abstract

The Clock gating reduces dynamic power dissipation in synchronous circuits. The gating function is the process of filtering glitches from a block which is achieved by inserting clock gating cell. Clock gating logic uses strong and weak matching process, they are two kinds of factor form matching. The strong matching seeks for the matches which are externally present in the factored forms and the weak matching identifies matches that are implicit in the logic and they are hard to discover. The clock gating logic can be generalized by using a technique called a Wide Spread Adapting (WSA) clock gating technique which is a modified Boolean function technique. The WSA technique does the matching process by using a WSA algorithm. This WSA technique reduces the clocking signal and the gate pattern. Thus the proposed method achieves reduced clock gating which in turn reduces delay, power, gate count and area.