CPU controller optimization in HDL logic synthesis

Abstract

We present a procedure to optimize controllers of a CPU in a high-level description language (HDL) logic synthesis environment. The procedure is optimized for power and area efficiency of the controller. Applying the procedure on an actual controller of a RISC CPU, we realized up to 30% power as well as 20% area reduction compared to an unoptimized design. The procedure is applicable to any synthesizable HDL with symbolic state variables in its behavioral description.