Package Size Reduction & Solder Joint Reliability for High Density Semiconductor Packaging

Abstract

Semiconductor packaging development for high volume consumer products poses many unique challenges across several technical disciplines in order to deliver the performance, cost, and reliability targets demanded in today's markets. In this paper, we will focus on the challenges around implementing compact Plastic Ball Grid Array (PBGA) package solutions for semiconductor devices considering the interdependencies of printed circuit motherboard technology, motherboard assembly processes, and reliability requirements for the mobile personal computer market segment. The focus will be on interconnect density, package size and product requirements and strategies for balancing each of these considerations. The discussion includes an examination of the trade offs around various strategies for package size reduction and how they apply to different markets.