On the impact of technology scaling on mixed PTL/static circuits

Abstract

We present the impact of technology scaling on mixed PTL/static circuits and compare the results with that of domino and conventional static CMOS. The state-of-the-art technologies of 0.18 /spl mu/m, 0.13 /spl mu/m, and 0.1 /spl mu/m were used in the study with V/sub dd/ being scaled accordingly. The benchmark suite consists of 10 circuits of varying complexities and they are actual circuits used in a state-of-the-art 64-bit microprocessor in the form of either dynamic or static CMOS circuits. The objective of this work is to determine how performance and power consumption scales with technology scaling. Our experimental results show that the mixed PTL/static circuit style is a promising alternative in power and power-delay product while achieving comparable delay to the dynamic circuit style.