Fault-Masking Capabilities of Basic Circuit Structures

Abstract

In this work, we present a theoretical model, which allows computing the effective fault rate of basic, regular circuit structures by paper and pencil. It therefore is possible to compute the masking capabilities of a circuit in the modeling phase - before the circuit is implemented. It furthermore allows calculating how much a fault can propagate within a circuit, may it be transient or permanent. The result is the maximal vulnerability of a circuit on gate-level. As an example, we take addition, since it is an essential operation in nearly every computing system. Over the years, many different methods with different minimum constraints concerning area and time have been developed. Parallel prefix adders are very regular in their structure, so that their vulnerability can be easily computed. The result of the exemplary examination is a ranking concerning the masking capabilities of such adders.