A 70 MS/s 8-bit differential switched-current CMOS A/D converter using parallel interleaved pipelines

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings Pub Date : 1995-11-06 DOI:10.1109/TENCON.1995.496358

M. Bracey, W. Redman-White, J. Hughes, J. Richardson

引用次数: 13

Abstract

A 70 MS/s CMOS A/D converter is presented. Four double-sampling differential switched-current pipelines are used in a time interleaved structure to achieve a high sampling rate. Particular issues addressed are the matching of signal copies whilst maintaining full analogue bandwidth, and minimising signal corruption during propagation. The experimental converter is fabricated in a standard 0.8 /spl mu/m 5 V digital CMOS process without special options.

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采用并行交错管道的70ms /s 8位差分开关电流CMOS A/D转换器

介绍了一种70 MS/s的CMOS A/D转换器。采用时间交错结构，采用4条双采样差分开关电流管道，实现高采样率。解决的具体问题是信号副本的匹配，同时保持全模拟带宽，并尽量减少传播过程中的信号损坏。实验变换器采用标准的0.8 /spl mu/m 5 V数字CMOS工艺制作，无需特殊选择。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings

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