An Efficient Single and Double Error Correcting Block Codes with Low Redundancy for Digital Communications

M. L. Saini, V. Sharma, Ashok Kumar
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Abstract

In digital communication there are various single and double bit error correcting and detecting codes are available. The efficiency of an error correcting code is evaluated by its errors correction capabilities and redundancy. This paper presents a new single bit and double bit error correcting codes which have lower redundancy compare to the other existing codes. In this paper the number of parity bits over the message bits for Hamming, BCH,RS Code, and DEC are examined and overhead is calculated. The proposed codes having less parity bits compared to other existing and having up to double bit error correction capabilities and minimize the encoding/decoding time delay.
数字通信中一种高效的低冗余单、双纠错分组码
在数字通信中,有各种各样的单、双比特纠错和检测码。纠错码的效率是通过纠错能力和冗余度来评价的。本文提出了一种新的单比特和双比特纠错码,与现有码相比,它们具有较低的冗余度。本文研究了汉明码、BCH码、RS码和DEC码的消息位上的奇偶校验位数,并计算了开销。与其他现有代码相比,所提出的代码具有更少的奇偶校验位,并且具有高达双比特的纠错能力,并且最大限度地减少编码/解码时间延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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