N. Farid, A. Nigam, S. A. E. A. Rahim, S. Hassan, R. Sanusi, A. Rahim
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引用次数: 0
Abstract
A miniature 40 GHz transceiver and radio front-end designed and simulated using a 0.13-μm RF CMOS process for Radio-over-Fiber applications is presented in this paper. The transceiver employs a direct-conversion architecture. The radio is designed for a frequency division duplex (FDD) communications system. PHY layer data rates as high as 1.5 Gbps on a wireless link are feasible using this radio design. The phase-locked-loop (PLL) and supporting digital circuits however, are not included. The receiver shows a power gain of about 41 dB with a LNA noise figure of 7 dB. The transmitter achieves a conversion gain of about 40.7 dB and an output P1dB of 10.7 dBm.