TD-SCDMA system frequency synthesizer design

Abstract

This paper give a design of a TD-SCDMA frequency synthesizer using multi-ring phase-locked loop, its output frequency has the very good precision and stability.The specific circuit is simulation using 0.5 um BICMOS technology and Cadence SpectreRF. The performance of whole frequency synthesizer is: its output frequency range is 2010 MHz - 2025 MHz, the frequency changing of stride is 200 KHz, the frequency locking time is smaller than 20 us, the power voltage is 3.3 V, the power consumption is 63.26 mW.