Reversible implementation of novel multiply accumulate (MAC) unit

Abstract

In almost all the Digital Signal Processing (DSP) applications, the vital operations involve multiplications and accumulations. Consequently, there is a demand for dedicated hardware in processors to enhance the speed with which these multiplications and accumulations are performed. In the present world of irreversible circuits, the Multiply Accumulate Unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the Accumulator all in a single clock cycle. On the other hand, implementation of digital circuits in reversible logic is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, we propose a novel Reversible Multiply Accumulate (MAC) unit. We also build a Reversible Vedic MAC unit and compare various possible implementations of the reversible MAC unit in terms of Quantum Cost, number of Garbage Outputs and Depth.