An optimal architecture of BCH decoder

Abstract

An optimal architecture for decoding BCH code is presented in this paper. This design uses a new architecture for syndrome computation to avoid multiplication operation, a Modified Direct Solution Algorithm to reduce the time and area consumption, an inverse error locator polynomial to avoid inverse operation in Chien Search, a new architecture for Chien Search and Error Correction using Finite Field Multiplier (FFM) called power FFM and constant FFM, and a manipulation bit method to reduce the number of XOR gates.