Estimation of Large-Signal Output Capacitance of a Power Transistor

Abstract

We introduce two experimental methods for estimation of the large-signal output admittance of a power FET. One relies on a local linearization of dependency of the output current on the output voltage. This method is suitable for technology evaluation and model verification. The other one derives the output admittance from the shape of contours of constant output voltage and provides the average value for a given voltage swing. The latter estimator can serve as a target for optimization of output matching networks. As the example of an LDMOS transistor shows, both methods yield consistent results.